FIG. 1 shows a typical active matrix display. Such a display is made up of a matrix 2 of picture elements (pixels), arranged in M rows and N columns. Each pixel row [column] is connected to a respective row [column] electrode, with the column electrodes being connected to the N outputs of a data driver 4 and the row electrodes being connected to the M outputs of a scan driver 6. The circuit of a typical pixel in a liquid crystal display (LCD) is shown in FIG. 2. The pixel comprises a display element 14 which is connected in parallel to a storage capacitor 16 via a common node 12 (also referred to below as a “charge storage node” or “storage node”). The other terminal of the storage capacitor 16 is connected to a common electrode 18, which may in use act as a capacitor bias line. The display element may comprise a pixel electrode which is electrically connected to the charge storage node 12 (and in this case the pixel electrode may constitute the charge storage node 12), and the other terminal of the display element 14 is connected to a counter plate electrode 20. The charge storage node 12 is also connected to the drain of a transistor 10. The source of transistor 10 is connected to the drain of a transistor 8. The source of transistor 8 is connected to a common source line 9 which is driven by one of the outputs from the data driver 4. The gates of 2 series connected transistor 8, 10 are connected together to a gate line 11 which is common to all the pixels of the row and which is connected to a respective output of the scan driver 6.
In use, rows of pixel display data are supplied by the data driver 4 to the source electrodes 9 in synchronism with scan pulses which are supplied by the scan driver 6 to the gate lines 11 in a cyclically repeating sequence. Thus the row of pixels are refreshed one at a time until all of the rows have been refreshed so as to complete the refreshing of a frame of display data. The process is then repeated for the next frame of data.
When the gate line 11 of each pixel receives a scan pulse from the scan driver 6, the voltage on the source electrode 9 causes the storage capacitor 16, and the pixel electrode of the display element, to be charged. When the scan pulse is removed, the transistors 8, 10 isolate the pixel electrode and the storage capacitor from the source electrode 9 so that the optical property of the associated display element 14 corresponds to the stored voltage across the display element 14 until it is refreshed during the next frame. (The voltage across the display element 14 is not necessarily equal to the voltage across the storage capacitor 16, since the counter plate electrode 20 of the display element 14 and the second plate 18 of the storage capacitor 16 may be at different potentials to one another.)
Methods of using capacitive coupling to the pixel electrode in active matrix displays, in order to apply an offset to the data signal voltage, both to minimise the range of signal voltages which is required to produce a full range of pixel luminances from fully off to fully transmissive, and to provide a power efficient means of alternating the polarity of the voltage across the liquid crystal layer in each pixel regions every frame are also well known. Capacitively coupled driving, in which the signal data voltage is supplied to the pixel electrode from the source electrode 9, via transistors 8, 10, during the period the gate line 11 of each pixel receives a scan pulse from the scan driver 6, in order to charge the pixel electrode and storage capacitor 16 to the voltage of the data signal, and then after the scan pulse is removed, an offset is imposed to the data voltage on the pixel electrode via capacitive coupling to the pixel electrode of a second voltage applied to the second plate 18 of the storage capacitor 16, is described in EP0336570A1 (11 Oct. 1989) and U.S. Pat. No. 5,296,847 (22 Mar. 1994, Matsushita) and in Tsunashima et al, SID Digest '07, pp 1014-1017.
The isolation transistors 8, 10 are not perfect. They exhibit a finite leakage drain current as illustrated in FIG. 3 which shows the typical transfer characteristic of an NMOS transistor. The leakage current in the transistor is a function of the drain to source (Vds) and gate to source (Vgs) potentials.
The leakage current results in a degradation of the programmed pixel electrode voltage over time T according to Equation 1 where Vpix is the pixel electrode voltage, Ileak is the leakage current, Cs is the storage capacitance and Clc is display element capacitance.
                                          ⅆ            Vpix                                ⅆ            T                          =                  Ileak                      Cs            +            Clc                                              (        1        )            
The pixel electrode voltage degradation due to leakage current requires the display data to be rewritten to minimise image deterioration during the hold time. A frame refresh rate of 60 Hz is typical. This constant refreshing of the display results in significant power consumption. One approach to reducing this power consumption is to reduce the frame refresh rate. Frame rate reduction is only possible if the degradation of the pixel electrode voltage is reduced. Considering Equation 1, the pixel electrode voltage degradation can be reduced by either increasing the size of the storage capacitor 16 or reducing the leakage current. A larger storage capacitor 16 is not desirable since it would result in increased pixel area and also increased pixel electrode charging time during scanning of each row. Thus, the preferred approach to reducing the frame refresh rate is to reduce the leakage current.
One known technique for reducing the electric field induced leakage current is to replace the 2 series transistors 8 and 10 with 3 or more transistors in series. This is in order to further reduce the drain voltage for each transistor. It may be noted however that the common gate voltage means that the leakage current does not scale with the number of series transistors. Another known technique, shown in FIG. 4, is to use an additional hold capacitor 15 at the junction of the series connected transistors 8, 10. This technique does not provide sufficient reduction in leakage current to enable reduction of frame refresh rate.
FIG. 5(a) illustrates another technique to increase the hold time over several frames as disclosed in Japanese laid-open patent application No. 5-142573 (11 Jun. 1993). This technique involves “boot strapping”: a unity gain voltage gain amplifier 22 has its input connected to the charge storage node 12 and the pixel electrode and its output connected to the junction between transistors 8 and 10. In other words the circuit of FIG. 5(a) is provided with a feedback function through the unity gain voltage amplifier 22, so that the pixel electrode voltage appears at the junction of the series connected transistors 8 and 10. If the buffer amplifier 22 were ideal and drew no charge from the pixel electrode, leakage from the pixel electrode would be eliminated since the drain to source voltage of transistor 10 would be reduced to zero volts. Examples of buffer amplifier 22 circuits disclosed shown in FIG. 5(b) include a CMOS source follower circuit 24 that combines an NMOS transistor and a PMOS transistor, a CMOS 2 stage source follower circuit 26 and voltage follower circuit that uses an operational amplifier 28. All of the proposed implementations of the buffer amplifier 22 result in at least 2 additional transistors and 2 power supply lines which results in an increase in the pixel circuit area. The additional transistors will reduce the yield during the fabrication of the display. Further, the increased active pixel area limits the minimum achievable pixel size and therefore limits the maximum resolution of the display. If a display is of a transmissive or transflective type, the increased active area of the pixel results in reduced light transmission from the backlight through the pixels which reduces the brightness of the display.
U.S. Pat. No. 6,064,362 (16 May 2000) and U.S. Pat. No. 7,573,451 (11 Aug. 2009) disclose a pixel circuit with a feedback buffer amplifier which as in the Japanese laid-open patent application No. 5-142573 aims to reduce the leakage from the storage node. The buffer amplifier in both disclosures consists of at least 2 additional transistors.
The power consumption of each of these 3 previous pixel circuits is dominated by the power consumption of the buffer amplifier which will make a significant contribution to the total power consumption of the active matrix display.
Transistor Characteristics
FIG. 3 illustrates typical n-channel transistor input characteristics. As the gate voltage increases from a low value, the drain current initially increases exponentially—and then flattens out (meaning that the rate of increase of the drain current with gate voltage becomes lower for higher gate voltages). This exponentially increasing characteristic is the subthreshold region of the transistor operation. The figure also shows the dependence of the drain current on the drain potential. In the subthreshold region, the gate voltage has a significantly greater influence upon the drain current compared with the drain voltage. For example, 0.25V change in gate voltage results in 40 times change in the drain current whereas an 8V change in the drain voltage is necessary to achieve the same drain current change.